The present invention generally relates to a semiconductor device and a method of forming metal lines in the semiconductor device and, more particularly, to a semiconductor device and a method of forming metal lines in the semiconductor device, in which the capacitance of the metal lines can be reduced.
Presently, since semiconductor device have become highly integrated, the density of elements per unit area has been increased and the density of interconnection lines formed in a semiconductor device has also been increased. The interconnection line is connected to a source region, a drain region and a gate of a transistor, which is disposed several thousands of μm from the line, and functions to supply the power and transfer signals. The interconnection line is generally formed of a metal line. A metal line is frequently used as a local interconnection line between respective unit circuits.
However, there is a need for a semiconductor device structure having a multi-layered metal line. Thus, resistance existing between adjacent metal lines on the same layer or between respective metal lines, which are adjacent above and below, is increased. Accordingly, research has been made to reduce resistance of metal lines in a single or a multi-layered metal line structure.
However, if the height or width of a metal line is increased in order to reduce resistance of the metal line, the capacitance of the metal line is increased. This capacitance of the metal line can be further increased due to a hard mask with a high dielectric constant, which is used to form a metal line using a damascene process and subsequently remains between metal lines. These capacitance components degrade the electrical performance of a semiconductor device due to delay caused by RC, and further increase power consumption of the semiconductor device and also signal leakage.